In several network projects is setup EXOS Switches as a stack with L2 and L3 Functions. Especially MLAG in conjunction with Active Active VRRP is very popular.
Now i am searching for a technical documentation which explain me the packet flow in a stack. Which packets will be processed within the switches hardware ASIC. Which packets will go to the CPU. Which packets go to the Master. How are the packets distributed. What happens when a member is failed. How is the "virtual backplane" of a stack working. Whats the difference between a L2 and a L3 packetflow....
until now i do not get any documentation or technical paper which will explain that! This seems to be beyond the scope of Configuration Guide or GTAC Knowledge Base.