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    <title>topic [EXOS 33.5.2.118] 25G SFP28 ports permanently down after power outage on 7520-48Y-8C — tx_disable la in ExtremeSwitching (EXOS/Switch Engine)</title>
    <link>https://community.extremenetworks.com/t5/extremeswitching-exos-switch/exos-33-5-2-118-25g-sfp28-ports-permanently-down-after-power/m-p/121826#M23206</link>
    <description>&lt;DIV&gt;&lt;P&gt;Environment&lt;/P&gt;&lt;P&gt;— Core: Extreme Networks 7520-48Y-8C running EXOS 33.5.2.118-patch3-1&lt;/P&gt;&lt;P&gt;— Access: Extreme Networks 5520 / 5720 series&lt;/P&gt;&lt;P&gt;— Link: 25G SFP28 fiber between core and access switches&lt;/P&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;Problem&lt;/P&gt;&lt;P&gt;After any power outage (accidental or planned maintenance), the 25G SFP28 ports on the 7520 core switch that connect to 5520/5720 access switches via fiber go down and never come back up. No CLI command recovers them. The only workaround is physically moving the fiber cable to a different port on the 7520.&lt;/P&gt;&lt;P&gt;We opened a TAC case and received patch 33.5.2.118-patch3-1 but the issue persists. We reverse-engineered the firmware binary (.xos) and found two critical bugs.&lt;/P&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;Root cause — what we found inside the firmware&lt;/P&gt;&lt;DIV&gt;&lt;P&gt;Bug 1: tx_disable asserted on every cold boot&lt;/P&gt;&lt;P&gt;Inside&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;extr/hw-config/Extreme/7520/ports.yaml&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(extracted from rootfs.xos), all 48 SFP28 ports have this in their&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;module_init_ops:&lt;/P&gt;module_init_ops: - device: port_cpld_1 register: 0x1 bitmask: 0x0040 # tx_disable bit value: 1 # ← asserts TX_DISABLE on every cold boot&lt;P&gt;On cold boot EXOS applies these init ops first — asserting tx_disable=1 on all 48 SFP28 ports via the PORT CPLDs. EXOS is supposed to clear this bit during port init. If there is a race condition (remote switch still booting) or EXOS crashes mid-init, the bit stays latched and the port is physically dead. No CLI can recover it because the bit is set at CPLD hardware level.&lt;/P&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;P&gt;Bug 2: FEC mode not specified (CL74 vs CL91)&lt;/P&gt;&lt;P&gt;The&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;25G_PORT&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;definition has&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Fec: true&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;but no explicit FEC type. EXOS negotiates at runtime, causing mismatches between the 7520 and 5520/5720 access switches.&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;Field test results&lt;/P&gt;&lt;P&gt;We changed FEC configuration (CL74 / CL91) explicitly on the affected ports:&lt;/P&gt;&lt;P&gt;— Most 25G SFP28 ports came back up immediately → FEC mismatch confirmed (Bug 2).&lt;/P&gt;&lt;P&gt;— Ports&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;1&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;5&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;remained down even after the FEC fix. Both use bitmask&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0x0040&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(bit 6 of the low byte) for tx_disable in PORT_CPLD_1 registers 0x1 and 0x2 respectively. This specific bit position appears to latch high and does not clear through normal EXOS port enable/disable cycles → Bug 1 confirmed as an independent failure.&lt;/P&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;1. Has anyone else hit this on 7520 + 55xx / 57xx topologies with 25G fiber after a power cycle?&lt;/P&gt;&lt;P&gt;2. Is there a way to write directly to PORT_CPLD registers from the EXOS CLI to manually clear the tx_disable bit without rebooting? Something like:&lt;/P&gt;# Looking for something equivalent to: debug hal port 1 write cpld tx_disable 0 # or any undocumented EXOS debug command to clear CPLD bits directly&lt;P&gt;3. Any experience with FEC auto-negotiation issues between 7520 and 5520/5720? Which FEC mode (CL74 or CL91) should be set on both sides for 25G SR fiber?&lt;/P&gt;&lt;P&gt;4. Is anyone aware of a fixed firmware version that addresses the tx_disable module_init_ops bug in ports.yaml?&lt;/P&gt;&lt;/DIV&gt;</description>
    <pubDate>Fri, 22 May 2026 19:09:27 GMT</pubDate>
    <dc:creator>Joelramirez</dc:creator>
    <dc:date>2026-05-22T19:09:27Z</dc:date>
    <item>
      <title>[EXOS 33.5.2.118] 25G SFP28 ports permanently down after power outage on 7520-48Y-8C — tx_disable la</title>
      <link>https://community.extremenetworks.com/t5/extremeswitching-exos-switch/exos-33-5-2-118-25g-sfp28-ports-permanently-down-after-power/m-p/121826#M23206</link>
      <description>&lt;DIV&gt;&lt;P&gt;Environment&lt;/P&gt;&lt;P&gt;— Core: Extreme Networks 7520-48Y-8C running EXOS 33.5.2.118-patch3-1&lt;/P&gt;&lt;P&gt;— Access: Extreme Networks 5520 / 5720 series&lt;/P&gt;&lt;P&gt;— Link: 25G SFP28 fiber between core and access switches&lt;/P&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;Problem&lt;/P&gt;&lt;P&gt;After any power outage (accidental or planned maintenance), the 25G SFP28 ports on the 7520 core switch that connect to 5520/5720 access switches via fiber go down and never come back up. No CLI command recovers them. The only workaround is physically moving the fiber cable to a different port on the 7520.&lt;/P&gt;&lt;P&gt;We opened a TAC case and received patch 33.5.2.118-patch3-1 but the issue persists. We reverse-engineered the firmware binary (.xos) and found two critical bugs.&lt;/P&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;Root cause — what we found inside the firmware&lt;/P&gt;&lt;DIV&gt;&lt;P&gt;Bug 1: tx_disable asserted on every cold boot&lt;/P&gt;&lt;P&gt;Inside&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;extr/hw-config/Extreme/7520/ports.yaml&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(extracted from rootfs.xos), all 48 SFP28 ports have this in their&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;module_init_ops:&lt;/P&gt;module_init_ops: - device: port_cpld_1 register: 0x1 bitmask: 0x0040 # tx_disable bit value: 1 # ← asserts TX_DISABLE on every cold boot&lt;P&gt;On cold boot EXOS applies these init ops first — asserting tx_disable=1 on all 48 SFP28 ports via the PORT CPLDs. EXOS is supposed to clear this bit during port init. If there is a race condition (remote switch still booting) or EXOS crashes mid-init, the bit stays latched and the port is physically dead. No CLI can recover it because the bit is set at CPLD hardware level.&lt;/P&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;P&gt;Bug 2: FEC mode not specified (CL74 vs CL91)&lt;/P&gt;&lt;P&gt;The&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;25G_PORT&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;definition has&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Fec: true&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;but no explicit FEC type. EXOS negotiates at runtime, causing mismatches between the 7520 and 5520/5720 access switches.&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;Field test results&lt;/P&gt;&lt;P&gt;We changed FEC configuration (CL74 / CL91) explicitly on the affected ports:&lt;/P&gt;&lt;P&gt;— Most 25G SFP28 ports came back up immediately → FEC mismatch confirmed (Bug 2).&lt;/P&gt;&lt;P&gt;— Ports&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;1&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;5&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;remained down even after the FEC fix. Both use bitmask&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0x0040&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(bit 6 of the low byte) for tx_disable in PORT_CPLD_1 registers 0x1 and 0x2 respectively. This specific bit position appears to latch high and does not clear through normal EXOS port enable/disable cycles → Bug 1 confirmed as an independent failure.&lt;/P&gt;&lt;/DIV&gt;&lt;HR /&gt;&lt;DIV&gt;&lt;P&gt;1. Has anyone else hit this on 7520 + 55xx / 57xx topologies with 25G fiber after a power cycle?&lt;/P&gt;&lt;P&gt;2. Is there a way to write directly to PORT_CPLD registers from the EXOS CLI to manually clear the tx_disable bit without rebooting? Something like:&lt;/P&gt;# Looking for something equivalent to: debug hal port 1 write cpld tx_disable 0 # or any undocumented EXOS debug command to clear CPLD bits directly&lt;P&gt;3. Any experience with FEC auto-negotiation issues between 7520 and 5520/5720? Which FEC mode (CL74 or CL91) should be set on both sides for 25G SR fiber?&lt;/P&gt;&lt;P&gt;4. Is anyone aware of a fixed firmware version that addresses the tx_disable module_init_ops bug in ports.yaml?&lt;/P&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 22 May 2026 19:09:27 GMT</pubDate>
      <guid>https://community.extremenetworks.com/t5/extremeswitching-exos-switch/exos-33-5-2-118-25g-sfp28-ports-permanently-down-after-power/m-p/121826#M23206</guid>
      <dc:creator>Joelramirez</dc:creator>
      <dc:date>2026-05-22T19:09:27Z</dc:date>
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