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    <title>topic Aerohive AP550 U-Boot password? in ExtremeWireless (IQE)</title>
    <link>https://community.extremenetworks.com/t5/extremewireless-iqe/aerohive-ap550-u-boot-password/m-p/90158#M1116</link>
    <description>&lt;P&gt;How can I have this password?&lt;BR /&gt;Thank you!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;U-Boot SPL 2012.10 (Aug 21 2018 - 20:07:28)&lt;BR /&gt;DEV ID = 0xcf1e&lt;BR /&gt;PCIE CFG DEV ID = 0x8025&lt;BR /&gt;OTP offset(0x8): 0x78f01c01&lt;BR /&gt;OTP offset(0x9): 0xfe200818&lt;BR /&gt;OTP offset(0xa): 0xc01b0&lt;BR /&gt;OTP offset(0xb): 0x0&lt;BR /&gt;OTP offset(0xc): 0x4a00000&lt;BR /&gt;OTP offset(0xd): 0xffede230&lt;BR /&gt;OTP offset(0xe): 0x1035d17f&lt;BR /&gt;OTP offset(0xf): 0x3406&lt;BR /&gt;ProgramCoreRailVoltageFromOTPAVSCode entry&lt;BR /&gt;avs_code programmed 78f01c01&lt;BR /&gt;avs_code programmed right shifted 00000011 00000000&lt;BR /&gt;Setting core voltage &amp;nbsp;520e0020 0&lt;BR /&gt;ProgramCoreRailVoltageFromOTPAVSCode exit&lt;BR /&gt;NSP 32-bit DDR&lt;BR /&gt;SKU ID = 0x0&lt;BR /&gt;DDR type: DDR3&lt;BR /&gt;MEMC 0 DDR speed = 800MHz&lt;BR /&gt;PHY revision version: 0x00004005&lt;BR /&gt;ddr_init2: Calling soc_ddr40_set_shmoo_dram_config&lt;BR /&gt;ddr_init2: Calling soc_ddr40_phy_calibrate&lt;BR /&gt;C01. Check Power Up Reset_Bar&lt;BR /&gt;C02. Config and Release PLL from reset&lt;BR /&gt;C03. Poll PLL Lock&lt;BR /&gt;C04. Calibrate ZQ (ddr40_phy_calib_zq)&lt;BR /&gt;C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT&lt;BR /&gt;C06. DDR40_PHY_DDR3_MISC&lt;BR /&gt;C07. VDL Calibration&lt;BR /&gt;C07.1&lt;BR /&gt;C07.2&lt;BR /&gt;C07.4&lt;BR /&gt;C07.4.1&lt;BR /&gt;C07.4.4&lt;BR /&gt;VDL calibration result: 0x30000003 (cal_steps = 0)&lt;BR /&gt;C07.4.5&lt;BR /&gt;C07.4.6&lt;BR /&gt;C07.5&lt;BR /&gt;C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....&lt;BR /&gt;C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....&lt;BR /&gt;C10. Wait for Phy Ready...Done.&lt;BR /&gt;DDR phy calibration passed&lt;BR /&gt;Programming controller register&lt;BR /&gt;ddr_init2: MemC initialization complete&lt;BR /&gt;Validate Shmoo parameters stored in flash ..... OK&lt;BR /&gt;Press Ctrl-C to run Shmoo ..... skipped&lt;BR /&gt;Restoring Shmoo parameters from flash ..... done&lt;BR /&gt;Running simple memory test ..... OK&lt;BR /&gt;DeepSleep wakeup: ddr init bypassed 3&lt;BR /&gt;DDR Interface Ready&lt;BR /&gt;&amp;nbsp;NAND_FLASH_DEVICE_ID_ADDR = 18026194&lt;BR /&gt;Done that&lt;BR /&gt;Micron MT29F8G08ABACA, blocks per lun: 1000 lun count: 1&lt;BR /&gt;256 KiB blocks, 4 KiB pages, 27B OOB, 8-bit&lt;BR /&gt;NAND: &amp;nbsp; chipsize&amp;nbsp;&lt;BR /&gt;total 0 bad blocks,LIST:&lt;BR /&gt;now the up level will see a good flash chip no bad block which size is 40000000&lt;BR /&gt;before nvram partition, there are 0 bad blocks&lt;BR /&gt;1024 MiB&lt;BR /&gt;nand_spl_load_image size 0x800&lt;BR /&gt;read from 0x61000000 size 0x1000&lt;BR /&gt;nand_spl_load_image size 0x99a68&lt;BR /&gt;read from 0x60ffffc0 size 0x9a000&lt;BR /&gt;Jumping to U-Boot&lt;BR /&gt;image entry point: 0x61000000&lt;/P&gt;&lt;P&gt;U-Boot 2012.10 (Aug 21 2018 - 20:07:28)&lt;/P&gt;&lt;P&gt;DRAM: &amp;nbsp;512 MiB&lt;BR /&gt;WARNING: Caches not enabled&lt;BR /&gt;GPIO Init ... Done&lt;BR /&gt;Power Input Detection: POE AT Port 0, Drive GPIO17(USB 5V enable) success&lt;BR /&gt;NAND: &amp;nbsp; NAND_FLASH_DEVICE_ID_ADDR = 18026194&lt;BR /&gt;Done that&lt;BR /&gt;(ONFI), &amp;nbsp;MT29F8G08ABACAWP, blocks per lun: 1000 lun count: 1&lt;BR /&gt;256 KiB blocks, 4 KiB pages, 27B OOB, 8-bit&lt;BR /&gt;NAND: &amp;nbsp; chipsize&amp;nbsp;&lt;BR /&gt;total 0 bad blocks,LIST:&lt;BR /&gt;now the up level will see a good flash chip no bad block which size is 40000000&lt;BR /&gt;before nvram partition, there are 0 bad blocks&lt;BR /&gt;1024 MiB&lt;BR /&gt;MMC: &amp;nbsp; iproc_mmc: 0&lt;BR /&gt;Using default environment&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;==== Check PCIe port 0&lt;BR /&gt;PCIe port in RC mode&lt;BR /&gt;PCIE link=0&lt;/P&gt;&lt;P&gt;==== Check PCIe port 1&lt;BR /&gt;PCIe port in RC mode&lt;BR /&gt;PCIE link=1&lt;BR /&gt;membase 0x40000000 memlimit 0x48000000&lt;BR /&gt;pcie1 switching to GEN2&lt;BR /&gt;PCIe port in RC mode&lt;BR /&gt;PCIE link=1&lt;BR /&gt;membase 0x40000000 memlimit 0x48000000&lt;BR /&gt;In: &amp;nbsp; &amp;nbsp;serial&lt;BR /&gt;Out: &amp;nbsp; serial&lt;BR /&gt;Err: &amp;nbsp; serial&lt;BR /&gt;org axi_clk=600MHz&lt;BR /&gt;iproc_get_axi_clk: refclk(0x17d7840), ndiv(0x3c) pdiv(0x1) mdiv(0x3): AXICLK:(0x1dcd6500)&lt;BR /&gt;arm_clk=1200MHz, axi_clk=500MHz, apb_clk=125MHz, arm_periph_clk=600MHz&lt;BR /&gt;Enabling icache and dcache&lt;BR /&gt;Enabling l2cache&lt;BR /&gt;Net: &amp;nbsp; Registering eth&lt;BR /&gt;Broadcom BCM IPROC Ethernet driver 0.1&lt;BR /&gt;Using GMAC1 (0x18023000)&lt;BR /&gt;et0: ethHw_chipAttach: Chip ID: 0xcf1e; phyaddr: 0x1e&lt;BR /&gt;bcm_robo_attach: devid: 0xd&lt;BR /&gt;bcmiproc_eth-0&lt;BR /&gt;MAC address is b87c:f254:de40&lt;/P&gt;&lt;P&gt;Found BCM958522ER diag support&lt;BR /&gt;COM2 is not configured due to board type&lt;BR /&gt;COM3 is not configured due to board type&lt;BR /&gt;Reset TPM chip...&lt;BR /&gt;Reset AUTH chip...&lt;BR /&gt;Hit any key to stop autoboot: &amp;nbsp;0&amp;nbsp;&lt;BR /&gt;Password:&lt;/P&gt;</description>
    <pubDate>Thu, 25 Feb 2021 01:15:28 GMT</pubDate>
    <dc:creator>yodcoo</dc:creator>
    <dc:date>2021-02-25T01:15:28Z</dc:date>
    <item>
      <title>Aerohive AP550 U-Boot password?</title>
      <link>https://community.extremenetworks.com/t5/extremewireless-iqe/aerohive-ap550-u-boot-password/m-p/90158#M1116</link>
      <description>&lt;P&gt;How can I have this password?&lt;BR /&gt;Thank you!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;U-Boot SPL 2012.10 (Aug 21 2018 - 20:07:28)&lt;BR /&gt;DEV ID = 0xcf1e&lt;BR /&gt;PCIE CFG DEV ID = 0x8025&lt;BR /&gt;OTP offset(0x8): 0x78f01c01&lt;BR /&gt;OTP offset(0x9): 0xfe200818&lt;BR /&gt;OTP offset(0xa): 0xc01b0&lt;BR /&gt;OTP offset(0xb): 0x0&lt;BR /&gt;OTP offset(0xc): 0x4a00000&lt;BR /&gt;OTP offset(0xd): 0xffede230&lt;BR /&gt;OTP offset(0xe): 0x1035d17f&lt;BR /&gt;OTP offset(0xf): 0x3406&lt;BR /&gt;ProgramCoreRailVoltageFromOTPAVSCode entry&lt;BR /&gt;avs_code programmed 78f01c01&lt;BR /&gt;avs_code programmed right shifted 00000011 00000000&lt;BR /&gt;Setting core voltage &amp;nbsp;520e0020 0&lt;BR /&gt;ProgramCoreRailVoltageFromOTPAVSCode exit&lt;BR /&gt;NSP 32-bit DDR&lt;BR /&gt;SKU ID = 0x0&lt;BR /&gt;DDR type: DDR3&lt;BR /&gt;MEMC 0 DDR speed = 800MHz&lt;BR /&gt;PHY revision version: 0x00004005&lt;BR /&gt;ddr_init2: Calling soc_ddr40_set_shmoo_dram_config&lt;BR /&gt;ddr_init2: Calling soc_ddr40_phy_calibrate&lt;BR /&gt;C01. Check Power Up Reset_Bar&lt;BR /&gt;C02. Config and Release PLL from reset&lt;BR /&gt;C03. Poll PLL Lock&lt;BR /&gt;C04. Calibrate ZQ (ddr40_phy_calib_zq)&lt;BR /&gt;C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT&lt;BR /&gt;C06. DDR40_PHY_DDR3_MISC&lt;BR /&gt;C07. VDL Calibration&lt;BR /&gt;C07.1&lt;BR /&gt;C07.2&lt;BR /&gt;C07.4&lt;BR /&gt;C07.4.1&lt;BR /&gt;C07.4.4&lt;BR /&gt;VDL calibration result: 0x30000003 (cal_steps = 0)&lt;BR /&gt;C07.4.5&lt;BR /&gt;C07.4.6&lt;BR /&gt;C07.5&lt;BR /&gt;C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....&lt;BR /&gt;C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....&lt;BR /&gt;C10. Wait for Phy Ready...Done.&lt;BR /&gt;DDR phy calibration passed&lt;BR /&gt;Programming controller register&lt;BR /&gt;ddr_init2: MemC initialization complete&lt;BR /&gt;Validate Shmoo parameters stored in flash ..... OK&lt;BR /&gt;Press Ctrl-C to run Shmoo ..... skipped&lt;BR /&gt;Restoring Shmoo parameters from flash ..... done&lt;BR /&gt;Running simple memory test ..... OK&lt;BR /&gt;DeepSleep wakeup: ddr init bypassed 3&lt;BR /&gt;DDR Interface Ready&lt;BR /&gt;&amp;nbsp;NAND_FLASH_DEVICE_ID_ADDR = 18026194&lt;BR /&gt;Done that&lt;BR /&gt;Micron MT29F8G08ABACA, blocks per lun: 1000 lun count: 1&lt;BR /&gt;256 KiB blocks, 4 KiB pages, 27B OOB, 8-bit&lt;BR /&gt;NAND: &amp;nbsp; chipsize&amp;nbsp;&lt;BR /&gt;total 0 bad blocks,LIST:&lt;BR /&gt;now the up level will see a good flash chip no bad block which size is 40000000&lt;BR /&gt;before nvram partition, there are 0 bad blocks&lt;BR /&gt;1024 MiB&lt;BR /&gt;nand_spl_load_image size 0x800&lt;BR /&gt;read from 0x61000000 size 0x1000&lt;BR /&gt;nand_spl_load_image size 0x99a68&lt;BR /&gt;read from 0x60ffffc0 size 0x9a000&lt;BR /&gt;Jumping to U-Boot&lt;BR /&gt;image entry point: 0x61000000&lt;/P&gt;&lt;P&gt;U-Boot 2012.10 (Aug 21 2018 - 20:07:28)&lt;/P&gt;&lt;P&gt;DRAM: &amp;nbsp;512 MiB&lt;BR /&gt;WARNING: Caches not enabled&lt;BR /&gt;GPIO Init ... Done&lt;BR /&gt;Power Input Detection: POE AT Port 0, Drive GPIO17(USB 5V enable) success&lt;BR /&gt;NAND: &amp;nbsp; NAND_FLASH_DEVICE_ID_ADDR = 18026194&lt;BR /&gt;Done that&lt;BR /&gt;(ONFI), &amp;nbsp;MT29F8G08ABACAWP, blocks per lun: 1000 lun count: 1&lt;BR /&gt;256 KiB blocks, 4 KiB pages, 27B OOB, 8-bit&lt;BR /&gt;NAND: &amp;nbsp; chipsize&amp;nbsp;&lt;BR /&gt;total 0 bad blocks,LIST:&lt;BR /&gt;now the up level will see a good flash chip no bad block which size is 40000000&lt;BR /&gt;before nvram partition, there are 0 bad blocks&lt;BR /&gt;1024 MiB&lt;BR /&gt;MMC: &amp;nbsp; iproc_mmc: 0&lt;BR /&gt;Using default environment&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;==== Check PCIe port 0&lt;BR /&gt;PCIe port in RC mode&lt;BR /&gt;PCIE link=0&lt;/P&gt;&lt;P&gt;==== Check PCIe port 1&lt;BR /&gt;PCIe port in RC mode&lt;BR /&gt;PCIE link=1&lt;BR /&gt;membase 0x40000000 memlimit 0x48000000&lt;BR /&gt;pcie1 switching to GEN2&lt;BR /&gt;PCIe port in RC mode&lt;BR /&gt;PCIE link=1&lt;BR /&gt;membase 0x40000000 memlimit 0x48000000&lt;BR /&gt;In: &amp;nbsp; &amp;nbsp;serial&lt;BR /&gt;Out: &amp;nbsp; serial&lt;BR /&gt;Err: &amp;nbsp; serial&lt;BR /&gt;org axi_clk=600MHz&lt;BR /&gt;iproc_get_axi_clk: refclk(0x17d7840), ndiv(0x3c) pdiv(0x1) mdiv(0x3): AXICLK:(0x1dcd6500)&lt;BR /&gt;arm_clk=1200MHz, axi_clk=500MHz, apb_clk=125MHz, arm_periph_clk=600MHz&lt;BR /&gt;Enabling icache and dcache&lt;BR /&gt;Enabling l2cache&lt;BR /&gt;Net: &amp;nbsp; Registering eth&lt;BR /&gt;Broadcom BCM IPROC Ethernet driver 0.1&lt;BR /&gt;Using GMAC1 (0x18023000)&lt;BR /&gt;et0: ethHw_chipAttach: Chip ID: 0xcf1e; phyaddr: 0x1e&lt;BR /&gt;bcm_robo_attach: devid: 0xd&lt;BR /&gt;bcmiproc_eth-0&lt;BR /&gt;MAC address is b87c:f254:de40&lt;/P&gt;&lt;P&gt;Found BCM958522ER diag support&lt;BR /&gt;COM2 is not configured due to board type&lt;BR /&gt;COM3 is not configured due to board type&lt;BR /&gt;Reset TPM chip...&lt;BR /&gt;Reset AUTH chip...&lt;BR /&gt;Hit any key to stop autoboot: &amp;nbsp;0&amp;nbsp;&lt;BR /&gt;Password:&lt;/P&gt;</description>
      <pubDate>Thu, 25 Feb 2021 01:15:28 GMT</pubDate>
      <guid>https://community.extremenetworks.com/t5/extremewireless-iqe/aerohive-ap550-u-boot-password/m-p/90158#M1116</guid>
      <dc:creator>yodcoo</dc:creator>
      <dc:date>2021-02-25T01:15:28Z</dc:date>
    </item>
    <item>
      <title>Re: Aerohive AP550 U-Boot password?</title>
      <link>https://community.extremenetworks.com/t5/extremewireless-iqe/aerohive-ap550-u-boot-password/m-p/90159#M1117</link>
      <description>&lt;P&gt;Hello, unfortunately we can’t give out the bootloader password. If you have support, you’ll want to file a support ticket to request a screen share time so a technician can enter that password for you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If you do not have support, please let me know and you and I can schedule a screen share time so I can enter the password for you instead. If you need any technical assistance beyond the bootloader password, you’ll need to file a support case.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 26 Feb 2021 00:54:51 GMT</pubDate>
      <guid>https://community.extremenetworks.com/t5/extremewireless-iqe/aerohive-ap550-u-boot-password/m-p/90159#M1117</guid>
      <dc:creator>SamPirok</dc:creator>
      <dc:date>2021-02-26T00:54:51Z</dc:date>
    </item>
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