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U-Boot SPL 2012.10 (Aug 21 2018 - 20:07:28)
DEV ID = 0xcf1e
PCIE CFG DEV ID = 0x8025
OTP offset(0x8): 0x78f01c01
OTP offset(0x9): 0xfe200818
OTP offset(0xa): 0xc01b0
OTP offset(0xb): 0x0
OTP offset(0xc): 0x4a00000
OTP offset(0xd): 0xffede230
OTP offset(0xe): 0x1035d17f
OTP offset(0xf): 0x3406
ProgramCoreRailVoltageFromOTPAVSCode entry
avs_code programmed 78f01c01
avs_code programmed right shifted 00000011 00000000
Setting core voltage 520e0020 0
ProgramCoreRailVoltageFromOTPAVSCode exit
NSP 32-bit DDR
SKU ID = 0x0
DDR type: DDR3
MEMC 0 DDR speed = 800MHz
PHY revision version: 0x00004005
ddr_init2: Calling soc_ddr40_set_shmoo_dram_config
ddr_init2: Calling soc_ddr40_phy_calibrate
C01. Check Power Up Reset_Bar
C02. Config and Release PLL from reset
C03. Poll PLL Lock
C04. Calibrate ZQ (ddr40_phy_calib_zq)
C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT
C06. DDR40_PHY_DDR3_MISC
C07. VDL Calibration
C07.1
C07.2
C07.4
C07.4.1
C07.4.4
VDL calibration result: 0x30000003 (cal_steps = 0)
C07.4.5
C07.4.6
C07.5
C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....
C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....
C10. Wait for Phy Ready...Done.
DDR phy calibration passed
Programming controller register
ddr_init2: MemC initialization complete
Validate Shmoo parameters stored in flash ..... OK
Press Ctrl-C to run Shmoo ..... skipped
Restoring Shmoo parameters from flash ..... done
Running simple memory test ..... OK
DeepSleep wakeup: ddr init bypassed 3
DDR Interface Ready
NAND_FLASH_DEVICE_ID_ADDR = 18026194
Done that
Micron MT29F8G08ABACA, blocks per lun: 1000 lun count: 1
256 KiB blocks, 4 KiB pages, 27B OOB, 8-bit
NAND: chipsize
total 0 bad blocks,LIST:
now the up level will see a good flash chip no bad block which size is 40000000
before nvram partition, there are 0 bad blocks
1024 MiB
nand_spl_load_image size 0x800
read from 0x61000000 size 0x1000
nand_spl_load_image size 0x99a68
read from 0x60ffffc0 size 0x9a000
Jumping to U-Boot
image entry point: 0x61000000
U-Boot 2012.10 (Aug 21 2018 - 20:07:28)
DRAM: 512 MiB
WARNING: Caches not enabled
GPIO Init ... Done
Power Input Detection: POE AT Port 0, Drive GPIO17(USB 5V enable) success
NAND: NAND_FLASH_DEVICE_ID_ADDR = 18026194
Done that
(ONFI), MT29F8G08ABACAWP, blocks per lun: 1000 lun count: 1
256 KiB blocks, 4 KiB pages, 27B OOB, 8-bit
NAND: chipsize
total 0 bad blocks,LIST:
now the up level will see a good flash chip no bad block which size is 40000000
before nvram partition, there are 0 bad blocks
1024 MiB
MMC: iproc_mmc: 0
Using default environment
==== Check PCIe port 0
PCIe port in RC mode
PCIE link=0
==== Check PCIe port 1
PCIe port in RC mode
PCIE link=1
membase 0x40000000 memlimit 0x48000000
pcie1 switching to GEN2
PCIe port in RC mode
PCIE link=1
membase 0x40000000 memlimit 0x48000000
In: serial
Out: serial
Err: serial
org axi_clk=600MHz
iproc_get_axi_clk: refclk(0x17d7840), ndiv(0x3c) pdiv(0x1) mdiv(0x3): AXICLK:(0x1dcd6500)
arm_clk=1200MHz, axi_clk=500MHz, apb_clk=125MHz, arm_periph_clk=600MHz
Enabling icache and dcache
Enabling l2cache
Net: Registering eth
Broadcom BCM IPROC Ethernet driver 0.1
Using GMAC1 (0x18023000)
et0: ethHw_chipAttach: Chip ID: 0xcf1e; phyaddr: 0x1e
bcm_robo_attach: devid: 0xd
bcmiproc_eth-0
MAC address is b87c:f254:de40
Found BCM958522ER diag support
COM2 is not configured due to board type
COM3 is not configured due to board type
Reset TPM chip...
Reset AUTH chip...
Hit any key to stop autoboot: 0
Password:
