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EXOS Stacking - How are the packets handled ?

EXOS Stacking - How are the packets handled ?

M_Nees
Contributor III
In several network projects is setup EXOS Switches as a stack with L2 and L3 Functions. Especially MLAG in conjunction with Active Active VRRP is very popular.

Now i am searching for a technical documentation which explain me the packet flow in a stack. Which packets will be processed within the switches hardware ASIC. Which packets will go to the CPU. Which packets go to the Master. How are the packets distributed. What happens when a member is failed. How is the "virtual backplane" of a stack working. Whats the difference between a L2 and a L3 packetflow....

until now i do not get any documentation or technical paper which will explain that! This seems to be beyond the scope of Configuration Guide or GTAC Knowledge Base.

Regards
3 REPLIES 3

M_Nees
Contributor III
Hi Stephan,
thanks for your information about that. That brings light into my darkness.

Do you know any kind of Extreme Manual that contain deeper view such like the above. It is not possible to explain the whole technical story in 4 or 5 sentences. i am interested to understand more of the internal way EXOS stacking / packet handling is working.

Do you have anything for me ??? Other vendor will porvide me such information at there documentation portals.

Regards

Stephane_Grosj1
Extreme Employee
Hi,

for L2, all packets are processed in HW: unicast or not. Eventually, some may be flooded (unknown unicast), but still in HW.
for L3, packets may be slow-path forwarded if you have some HW table full situation, or if the packets are specific (IP options set, for example).

Master CPU will handle management and protocols. That's what goes to the Master. Anything else goes directly to the destination (that can be multiple depending on the packet type). The unit member receiving a packet does the lookup, find the destination port and send the packet directly to it. If it's on another unit member, the fastest path to it is used (it depends on the # hops and each stacking link speed - as you may have different stacking speed in your stack). Of course Master CPU will have the burden to generates ARP (if L3), and things like that.

Your stack is using a ring, and both links on each member are forwarding for unicast traffic. One link on one unit is blocked for broadcast, and one link is blocked per multicast groups. EXOS only output what port is blocked for broadcast.

If a stacking link fails, or a unit fails, failover happens very quickly and is impacting only the traffic that was flowing on that link at that time.

M_Nees
Contributor III
Nobody out there which can clarify this or does some good documentation ?! Nobody out there which afflicted from the same questions ?
GTM-P2G8KFN